The present invention relates to a semiconductor device comprising a metal-insulator-semiconductor field effect transistor and, more specifically, to a power MISFET structure with high withstand voltage.
Recently, power IC's have been developed that integrate a MOSFET or insulated gate field effect transistor having a withstand voltage of several hundred volts and having a current capacity or withstand capability of several amperes, with a control circuit operating at a voltage of around 5 volts. Some of the developed power IC's have already been used in switching power supplies as disclosed in the Japanese Laid Open Patent Application No. S63-314869.
FIGS. 11 and 12 show a power IC disclosed in the Japanese Laid Open Patent Application No. H04-309920 by the inventors of the present invention. This power IC comprises a power MOSFET portion 1 and a control circuit portion 2 formed on a semiconductor chip. The sectional structure of the power MOSFET portion 1 is shown in FIG. 12. The power MOSFET portion 1 is a transverse DMOSFET comprising a MOS portion 25 and a drain portion 26 formed on an N-type well layer 11 disposed on a P-type semiconductor substrate 10. In the MOS portion 25, a pair of mutually separated P-type base layers 12 are formed, at whose surface an inversion layer (channel) is to be formed. An N.sup.+ -type source layer 13 and a P.sup.+ -type base contact layer 14 are disposed on the first P-type base layer 12. A poly-silicon gate electrode 15 bridging a pair of the source layers 13 is disposed on a gate insulation film (not shown). A source electrode 16 is connected with the source layers 13 and the base contact layers 14 through contact holes. The source electrode 16 has a field plate portion 16a protruding toward the drain portion 26 to create a high withstand voltage structure which relieves concentration of an electric field to an edge portion of the source layer 12. A reference numeral 17 designates an inter-layer insulation film, and 18 a passivation film.
In the drain portion 26, an N-type base layer 19 functions as a drain layer and is disposed on the N-type well layer 11. An N.sup.+ -type base contact layer 20 is in turn disposed on a portion of the N-type base layer 19. A drain electrode 21 is connected to the base contact layer 20 through a contact hole. The drain electrode 21 has a field plate portion 21a protruding toward the MOS portion 25 to create a high withstand voltage structure which relieves concentration of an electric field to an edge portion of the N-type base layer 19. A reference numeral 22 designates a thick insulation film such as LOCOS local oxide film. Between the MOS portion 25 and the drain portion 26, the second P-type base layer 23 is disposed on the N-type well layer 11 bridging the first P-type base layer 12 and the N-type base layer 19.
The second P-type base layer 23, or offset layer, lies between the MOS portion 25, including the underlying part and periphery of the gate electrode 15, and the drain portion 26, including the underlying part and periphery of the drain electrode 21. Thus, the second P-type base layer 23 is folded like comb teeth on the chip as shown in FIG. 11 and defines the boundary between the MOS portion 25 and the drain portion 26. The MOS portion 25, including the source pad 16b, is formed outside the boundary, i.e., the second P-type base layer 23, while the drain portion 26, including the drain pad 21b, is formed inside the boundary.
The reason for connecting the P-type base layer 23 to the P-type base layer 12 and extending the P-type base layer 23 into the edge portion of the N-type base layer 19, is as follows:
(1) When the MOSFET is ON, i.e., when the gate electrode 15 is biased with a potential higher than the source potential and the drain electrode with a high potential, an inversion layer is formed in the surface of the first base layer 12 underneath the gate electrode 15, while electrons, the majority carrier, flow out from the source layer 13 to the N-type well layer 11 under the gate electrode 15 through the channel. Similar to a vertical DMOSFET, the electrons flow downward in the N-type well layer 11 under the gate electrode 15, and then flow horizontally along the N-type well layer 11 to the N-type base or drain layer 19. Though the electrons are absorbed by the drain electrode 21 through the drain contact layer 20, when a large current flows in a DMOSFET which lacks the P-type base layer 23 on the N-type well layer 11 as a horizontal current path, hot electrons are injected into the insulation film 22 to cause time dependent variation of the electric field and degradation of the reliability of the device. However, the influence of the hot electrons can be ignored, because the junction between the P-type base layer 23 and the N-type well layer 11 is reverse-biased and the electrons flowing in the N-type well layer 11 do not contact the insulation film 22 as long as the P-type base layer 23 exists. PA1 (2) When the MOSFET is OFF, i.e., when the forward current flow is shut off, with the gate electrode 15 biased with low potential, e.g., a source potential or ground potential, while the drain electrode 21 is biased with high potential, then, since the junction between the first P-type base layer 12 or the second P-type base layer 23 and the N-type well layer 11, and the junction between the N-type well layer 11 and the P-type semiconductor substrate 10 are reverse-biased, depletion layers spread from the junctions into the N-type well layer 11. Taking into consideration the depletion layers spreading from the first P-type base layer 12 and the substrate 10 on the side of the N-type base layer (drain layer) 19, the inside of the well layer 11 near under the gate electrode 15 is pinched off and the current path is shut off as in a JFET. Additionally, if the depletion layers spread from the second P-type base layer 23 and the substrate 10 under consideration, the inside of the well layer 11 under the second P-type base layer 23 is pinched off, shutting off the current path as in a JFET.
Thus, the current path is assuredly shut off inside the well layer 11 by the JFET effect of the second P-type base layer 23 when the reverse bias voltage is applied. Therefore, for securing the withstand voltage, it is not necessary to elongate the offset region, i.e., the region between the first base layer 12 and the N-type base layer 19, with low dopant concentrations of the N-type well layer 11, and the MOSFET can be provided with a higher withstand voltage and its ON-resistance can be lowered by doping the N-type well layer 11 with relatively high impurity concentrations.
However, the above described transverse DMOSFET provided with a second base layer 23 which covers the offset region has several drawbacks. First, though the pinch off occurs under the second base layer 23 when the forward current flow is shut off, avalanche breakdown occurs in region 24 as the drain potential is further raised, because of the concentration of an electric field E, the direction of which is indicated by an arrow in FIG. 12, in the junction portion 24 under the edge of the field plate portion 21a between the second base layer 23 under the N.sup.- -type well layer 11. Avalanche breakdown also occurs because the region 24 (hereinafter referred to as "breakdown generation portion"), located near the edge of the field plate portion 21a and easily affected by edge electric field, is a portion in which the composite electric field E constituted of a vertical electric field between the second base layer 23 and the N-type well layer 11 and a horizontal electric field between the second base layer 23 and the N-type base layer 19 are at the maximum. As avalanche breakdown occurs in the region 24 in the rate determining manner as described above, some of the produced electrons are readily injected into the oxide film 22 and vary, as time elapses, the electric field distribution near the location at which the avalanche breakdown has occurred. The variation of the electric field distribution varies the breakdown voltage with elapse of time and deteriorates stability and reliability of the device. The avalanche breakdown spot and the breakdown voltage are easily varied by the diffusion extent and the dopant concentrations. Though the holes produced by the avalanche breakdown flow horizontally to a not shown PN junction separation layer, or isolation layer, they diverge before reaching the isolation layer and deteriorate the stability of the device, because the power MOSFET portion 1 occupies a large part of the chip area, as shown in FIG. 11.
In view of the foregoing, an object of the present invention is to provide a semiconductor device comprising a highly reliable MIS transistor which suppresses time dependent variation of its withstand voltage by adopting a semiconductor structure which facilitates fixing the breakdown voltage at a predetermined value.